The present invention is generally in the field of semiconductor testing. More specifically, the present invention is in the field of reliability testing of semiconductor dice.
Semiconductor die reliability testing is a necessary process to ensure reliable semiconductor products, such as microprocessors and memory arrays. A typical semiconductor die for a microprocessor or memory array may comprise millions of transistors. Any failure of an individual transistor can cause the entire semiconductor die to fail. The reliability of the semiconductor die can be measured by the projected lifetime of the semiconductor die, which semiconductor die manufacturers typically determine by utilizing test structures having much smaller sizes than the semiconductor die.
According to a conventional process utilized to determine the lifetime of a semiconductor die, lifetimes for different size test structures can be obtained by testing the failure rate of gate oxide of transistors in the test structures at a particular test gate voltage. The lifetimes of the test structures can be plotted against the size of the test structures to obtain a line having a slope equal to xe2x80x9cn,xe2x80x9d which is a scaling factor. The lifetime of the semiconductor die can be calculated using the equation:                                           t            TC                                                           t              prod                                      =                              (                                                                             A                  TC                                                                                               A                  prod                                                      )                                              -              1                        /            β                                              equation        ⁢                  xe2x80x83                ⁢                  (          1          )                    
where xe2x80x9ctTCxe2x80x9d is the lifetime of a test structure, xe2x80x9ctprodxe2x80x9d is the lifetime of a product, i.e. the semiconductor die, xe2x80x9cATCxe2x80x9d is the area of the test structure, xe2x80x9cAprodxe2x80x9d is the area of the product, and xe2x80x9cxcex2xe2x80x9d is the Weibull slope, which is equal to the reciprocal of scaling factor n. However, the scaling factor is determined in the above conventional process at one test gate voltage, which is different than an actual operating gate voltage of the product, i.e. the semiconductor die. By way of background, the lifetime of a semiconductor die generally goes down as bias voltage is increased across gate oxide in the semiconductor die. Thus the lifetime of a semiconductor die is a function of lo bias voltage across gate oxide in the semiconductor die. Thus, since scaling factor n is determined in the above conventional process without accounting for change in bias voltage, xcex2 obtained using the above process will not be accurate. As a result, the lifetime of the semiconductor die determined by the above process will also lack accuracy.
Thus, there is a need in the art for a method for determining a Weibull slope that provides adjustment for variations in gate bias voltage, where the Weibull slope can be used to determine a lifetime of a semiconductor die.
The present invention is directed to determining a Weibull slope having a bias voltage variation adjustment. The present invention addresses and resolves the need in the art for a method for determining a Weibull slope that provides adjustment for variations in gate bias voltage, where the Weibull slope can be used to determine a lifetime of a semiconductor die.
According to one exemplary embodiment, a method for determining a Weibull slope at a specified bias voltage comprises a step of performing a number of groups of failure tests on a test structure to determine a number of groups of test data, where each of the groups of failure tests is performed at a respective one of a number of test bias voltages, and where each group of failure tests corresponds to a respective group of test data. The test structure may be an array of MOS transistors, for example. The specified bias voltage may be, for example, an operating gate bias voltage of a semiconductor die. The method further comprises utilizing the number of groups of test data to determine a scaling line. For example, the scaling line may be determined by utilizing each of the groups of test data to determine a respective failure line, determining a number of failure line slopes, where each of the failure line slopes corresponds to a respective failure line, and utilizing the number of failure line slopes to determine the scaling line.
According to this exemplary embodiment, the method further comprises utilizing the scaling line to determine the Weibull slope at the specified bias voltage. The method may further comprise utilizing the Weibull slope to determine a lifetime of the semiconductor die. Other features and advantages of the present invention will become more readily apparent to those of ordinary skill in the art after reviewing the following detailed description and accompanying drawings.